In a NAND memory array, all the memory cells in a page are programmed and read at the same time. So, in principle, the larger the page size, the greater the parallelization of the program/read operations. This will result in higher data throughput provided that the program/read operations themselves are not greatly degraded as a result of the larger page size. Historically, NAND page size has steadily increased from generation to generation in order to support higher and higher data throughput, even though the program/read timing has been degrading in general. The increases in page size are possible due to the fact that the cell pitch scales down from generation to generation.
A page will include all of the memory cells (in an all-bitline (ABL) architecture) or half of the memory cells (in a shielded bitline (SBL) architecture) along a single wordline in an array plane. Limitations of a size of a die limit the absolute length of the wordlines (i.e., the width of an array plane). That sets an upper limit on the number of memory cells that can be placed along a single wordline. So, with matched bitline and cell pitch, the page size that can be supported is limited for a given cell pitch.
The limitation on page size has not been a significant issue for NAND because the cell pitch has been steadily decreasing from generation to generation as a result of cell scaling, which enables page size increases within the die-size limitation. However, as conventional NAND scaling comes to an end, future NAND scaling may be achieved by three-dimensional (3-D) NAND memory arrays.
In 3-D NAND memory arrays, the cell size in the wordline direction is limited by a cell channel thickness (in the form of a pillar or line), a gate stack thickness (tunnel oxide, charge trapping layer, and blocking oxide), and a gate electrode thickness. As a result, the cell pitch in the wordline direction will be significantly bigger than conventional, i.e., 2-D NAND memory arrays. While density-wise, the larger cell pitch can be compensated by the fact that multiple layers of cells are stacked on top of one another, the page size will have to come down because of the larger cell pitch, with everything else being equal (die architecture, package size, etc.). Thus, the data throughput of 3-D NAND memory arrays may be significantly degraded compared to 2-D NAND memory arrays, limiting their competitiveness.